1. Field of the Invention
The present invention relates to a television receiver in which a video signal is digitally processed and scanned at the frequency n times as high as that of the horizontal sync and, more particularly, to a synchronous deflection circuit generating the system clock and reference signals synchronized with the input horizontal sync signal.
2. Description of the Prior Art
Television receivers are being actively developed these days and there is an IDTV (Improved Definition TV) on the market in which a digital circuit is used in its video circuit in place of an analog circuit hitherto used for signal processing. With the aim to process the existing television signal into a picture of a higher quality, various types of signal processing techniques achieving a high quality picture are being studied and some are put into practice.
The signal processing techniques to achieve a high quality picture includes:
(1) Three-dimensional Y/C separation using a frame memory unit and a noise reducer.
(2) Multiple speed conversion to convert an interlace signal into a noninterlace signal.
(3) Vertical contour correction using a line memory unit.
Since such signal processing is required to be performed in a digital circuit with high accuracy, the provision of stabilized synchronous reproduction and a stable system clock becomes indispensable. As an example of such techniques, there is one disclosed in Ser. No. 248,375 (filed on Sep. 23, 1988), now U.S. Pat. No. 4,870,490 principle of the art will be briefly described below.
FIG. 1 is a block diagram showing a structure of a prior art television receiver, in which reference numeral 11 denotes an input terminal, 12 denotes a line comb filter, 13, 14, and 15 denote A/D converters, 16 denotes a color demodulation circuit, 17 and 18 denote frame comb filters, 19 and 20 denote multiple speed conversion circuits, 21, 22, and 23 denote D/A converters, 24 denotes a matrix video output circuit, 25 denotes a cathode ray tube, 26 denotes a sync separation circuit, 27 denotes a clock generation/synchronous deflection circuit, 28 denotes a digital signal processor, 30 denotes a write reference signal, 31 denotes a read reference signal, and 32 denotes a system clock.
Operations will be described below. A composite video signal input through the input terminal 11 is separated into a luminance signal (Y) and a chrominance signal (C) by the line comb filter 12. The separated chrominance signal (C) by the line comb filter 12 is separated into two color difference signals (R-Y, B-Y) by a color demodulation circuit 16. The thus obtained luminance signal (Y) and color difference signals (R-Y, B-Y) are delivered to the digital signal processor 28.
In the digital signal processor 28, the incoming luminance signal (Y) and color difference signals (R-Y, B-Y) are respectively converted into digital signals by the A/D converters 13, 14, and 15. The luminance signal (Y) converted to the digital signal is deprived of residual color signal and noise components by the frame comb filter 17. Then, the luminance signal (Y) is subjected to a multiple speed conversion in the multiple speed conversion circuit 19, whereby the signal, which has been of interlaced scanning lines, is given new scanning lines by interpolation put in between the original scanning lines. The luminance signal (Y) undergone the multiple speed converted is recovered to an analog signal by the D/A converter 21. On the other hand, the color difference signals (R-Y, B-Y) converted to digital signals, similar to the luminance signal (Y), are also deprived of residual luminance signal and noise components by the frame comb filter 18. Then, these signals, which have been of interlaced scanning lines, are given interpolating scanning lines put in between their original scanning lines, and thereby, these signals are converted to those with the multiple speed. Such color difference signals (R-Y, B-Y) converted so as to have the multiple speed are respectively recovered to analog signals by the D/A converters 22 and 23.
The thus obtained luminance signal (Y) and color difference signals (R-Y, B-Y) with the multiple speed are converted into RGB signals by the matrix video output circuit 24 and amplified with a predetermined gain and supplied to the cathode ray tube 25 as high quality video.
The composite video signal input through the input terminal 11 is also supplied to the sync separation circuit 26 and a horizontal sync signal and a vertical sync signal are separated therefrom. The horizontal sync signal of the separated sync signals is supplied to the clock generation/synchronous deflection circuit 27. The clock generation/synchronous deflection circuit 27 performs outputting of a system clock 32 (1820 f.sub.H), the write reference signal 30 (f.sub.H) for writing signals into the memory, and the read reference signal 31 (2 f.sub.H) for multi-speed conversion as well as deflection of the electron beam in the horizontal direction.
A prior art example of the clock generation/synchronous deflection circuit 27 will be described below with reference to FIG. 2. Referring to the figure, reference numeral 41 denotes an input terminal, 42 denotes a phase comparator (PD), 43 denotes a low-pass filter (LPF), 4 denotes a voltage-controlled oscillator (VCO), 45 denotes a 1/910 frequency divider, 46 denotes a horizontal output circuit, 47 denotes a flyback transformer (FBT), and 48 and 49 denote 1/2 frequency dividers.
The horizontal sync signal input through the input terminal 41 is supplied to the phase comparator (PD) 42 and therein it is compared with the other input and the result corresponding to the phase difference is output. The output of the phase comparator is filtered in the low-pass filter (LPF) 43 so as to be given a predetermined response characteristic and supplied to the voltage-controlled oscillator (VCO) 44. The voltage-controlled oscillator (VCO) 44 functions to vary its oscillating frequency (here, around 1820 f.sub.H) corresponding to the incoming voltage as the result of the phase comparison. The output oscillated thereby becomes the system clock 32 and it is supplied to both the digital signal processor and the 1/910 frequency divider 45.
The 1/910 frequency divider 45 divides the frequency of the incoming clock, thereby generating the reference signal necessary for the digital signal processor and the like. The read reference signal 31 is obtained by the frequency division of the system clock 32 in the 1/910 frequency divider 45, and by the frequency division of this signal in the 1/2 frequency divider 49 is obtained the write reference signal 30. The read reference signal undergone the 1/910 frequency division is further supplied to the horizontal output circuit 46 as the horizontal drive signal for the horizontal deflection system. The horizontal output circuit 46 amplifies the horizontal drive signal undergone the 1/910 frequency division and drives the horizontal deflection yoke as shown in FIG. 1 with the signal, thereby performing the horizontal scanning. At the same time, the voltage of the signal for driving the deflection yoke is stepped up by the flyback transformer (FBT) 47 so as to be used as high-voltage power sources. A flyback pulse generated on the secondary side of the flyback transformer is subjected to 1/2 frequency division in the 1/2 frequency divider 48 and supplied as a horizontal sync signal to the phase comparator (PD) 42.
Thus, the phase comparator (PD) 42 makes comparison of the phase of the horizontal sync signal input through the input terminal 41 with the phase of the flyback pulse generated in the horizontal deflection system and undergone the 1/2 frequency division. As a result, the horizontal deflection system shown in FIG. 2 performs feedback control so that the input signal and the horizontal deflection signal are kept in phase at all times.
In the above described prior art, no consideration has been made of the storage time (t.sub.s) in the horizontal output transistor of the horizontal output circuit 46 and surrounding transistors and, hence, there has been a problem that the horizontal center of the picture deviates as the temperature changes. This problem will be described below with reference to FIG. 3A to FIG. 3F.
FIG. 3A to FIG. 3F are waveform charts of signals in various points in the FIG. 1 and FIG. 2. When a video signal shown in FIG. 3A is output from the matrix video output circuit 24 and, at the same time, the horizontal drive signal shown in FIG. 3B is output from the 1/910 frequency divider 45, the horizontal output circuit 46 supplies the deflection current as shown in FIG. 3C to the horizontal deflection yoke, whereby scanning is performed. The flyback pulse then generated is in the position virtually corresponding to the retrace time as shown in FIG. 3D.
In bipolar transistors, generally, when they are used for switching and turned from ON to OFF, there is present a storage time (t.sub.s) causing a delay in the switching. The storage time tends to increase as the temperature rises. Therefore, when temperature rises, the deflection current and the flyback pulse are delayed by .DELTA.t.sub.s as shown in FIG. 3E and FIG. 3F, and as a result, the horizontal center of the picture is deviated. The situation at this time is shown in FIG. 4A and FIG. 4B. FIG. 4A shows a picture before the deviation occurs and FIG. 4B shows a picture after the deviation has occurred. As apparent from the figures, a picture image which has been observed up to that time goes off the screen as the horizontal center deviates with the lapse of time and increase in temperature.